Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its data values for some extended period without the application of power. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge-storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, such as a source select line and a drain select line.
A “column” refers to a group of memory cells that are commonly coupled to a local data line, such as a local bit line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. Each source select line is connected to a source line, while each drain select line is connected to a data line, such as column bit line.
Memory cells are sometimes programmed using program/erase operations, e.g., where such an operation might involve first erasing a memory cell and then programming the memory cell. For example, a plurality of memory cells, such as a string of memory cells, a plurality of strings of memory cells, etc., might be erased at once, e.g., during an erase operation, and then one or more of the erased memory cells might be programmed, e.g., during a program operation. A plurality of memory cells erased at once is sometimes called an erase block, for example.
For a NAND array, for example, a plurality of memory cells might sometimes be erased by grounding the access lines coupled to the plurality of memory cells and applying an erase voltage to a semiconductor over which the memory cells are commonly formed, and thus to the channels of the memory cells, to remove the charge from the charge-storage structures. More specifically, the charge is removed through Fowler-Nordheim tunneling of electrons from the charge-storage structure to the channel, resulting in an erase threshold voltage, e.g., an erase Vt, that can be less than zero.
An erase voltage is then applied to the plurality of memory cells to confirm whether the memory cells have been erased below an erase threshold voltage level. For example, an erase verify voltage might be applied to the access lines coupled to the plurality memory cells that are being erased. An erase voltage followed by an erase verify voltage might be referred to as an erase-and-verify cycle or simply as an erase cycle, and an erase operation might include one or more erase cycles to erase the plurality of memory cells. If any of the plurality of memory cells fail erase verification, the erase cycles may be repeated until the plurality of memory cells is erased or a certain number of erase cycles have occurred and the erasure is deemed to have failed.
A problem with erasing some flash memory devices is that different access lines in a given erase block can have faster or slower erase characteristics due to issues that can include, but are not limited to, different access line resistance, the physical placement of an access line in the memory array, and the access line coupling to the memory cells and other adjacent elements and access lines of the memory array. Because of this, slower erasing memory cells could get under erased (e.g., possibly causing additional erase cycles) and faster erasing memory cells could get over erased and overstressed (e.g., decreasing the lifespan of the affected memory cells and the endurance of the erase block).
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing erase operations.